1. Field of the Invention
This invention relates to the field of microprocessors and, more particularly, to microcode instruction mechanisms within microprocessors.
2. Description of the Relevant Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term "clock cycle" refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term "instruction processing pipeline" is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion. Although the pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally comprises fetching the instruction, decode the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
Microprocessor designers often design their products in accordance with the x86 microprocessor architecture in order to take advantage of its widespread acceptance in the computer industry. Because the x86 microprocessor architecture is pervasive, many computer programs are written in accordance with the architecture. X86 compatible microprocessors may execute these computer programs, thereby becoming more attractive to computer system designers who desire x86-capable computer systems. Such computer systems are often well received within the industry due to the wide range of available computer programs.
The x86 microprocessor architecture specifies a variable length instruction set (i.e. an instruction set in which various instructions employ differing numbers of bytes to specify that instruction). For example, the 80386 and later versions of x86 microprocessors employ between 1 and 15 bytes to specify a particular instruction. Instructions have an opcode, which may be 1-2 bytes, and additional bytes may be added to specify addressing modes, operands, and additional details regarding the instruction to be executed. Certain instructions within the x86 instruction set are quite complex, specifying multiple operations to be performed. For example, the PUSHA instruction specifies that each of the x86 registers be pushed onto a stack defined by the value in the ESP register. The corresponding operations are a store operation for each register, and decrements of the ESP register between each store operation to generate the address for the next store operation.
Often, complex instructions are classified as MROM instructions. MROM instructions are transmitted to a microcode instruction unit, or MROM unit, within the microprocessor, which decodes the complex MROM instruction and dispatches two or more simpler microcode instructions for execution by the microprocessor. The simpler microcode instructions corresponding to the MROM instruction are typically stored in a read-only memory (ROM) within the microcode instruction unit. The microcode instruction unit determines an address within the ROM at which the simpler microcode instructions are stored, and transfers the microcode instructions out of the ROM beginning at that address. Multiple clock cycles may be used to transfer the entire set of microcode instructions corresponding to the MROM instruction. The entire set of microcode instructions that effectuate the function of an MROM instruction is called a microcode sequence. Each MROM instruction may correspond to a particular number of microcode instructions dissimilar from the number of microcode instructions corresponding to other MROM instructions. Additionally, the number of microcode instructions corresponding to a particular MROM instruction may vary according to the addressing mode of the instruction, the operand values, and/or the options included with the instruction. The microcode unit issues the microcode instructions into the instruction processing pipeline of the microprocessor. The microcode instructions are thereafter executed in a similar fashion to other instructions. It is noted that the microcode instructions may be instructions defined within the instruction set, or may be custom instructions defined for the particular microprocessor.
Conversely, less complex instructions are decoded by hardware decode units within the microprocessor, without intervention by the microcode unit. The terms "directly-decoded instruction" and "fastpath instruction" will be used herein to refer to instructions which are decoded and executed by the microprocessor without the aid of a microcode unit. As opposed to microcode instructions which are reduced to simpler instructions which may be handled by the microprocessor, directly-decoded instructions are decoded and executed via hardware decode and functional units included within the microprocessor.
Microcode instructions that implement an MROM instruction may include branch microcode instructions. For example, a string instruction may include a loop of microcode instructions. A microcode loop is one or more microcode instructions that are repetitively executed a specific number of times. The specific number of iterations is called a loop count or string count. A microcode loop may include a branch instruction and a decrement instruction. Each iteration of the loop, the string count is decremented. If the string count is non-zero, the branch instruction branches to the top of the loop and the microcode instructions are dispatched again. Typically, microcode units implement static branch prediction. In other words, the branch prediction is determined during coding and does not change. In the case of a branch instruction of microcode loop, the branch instruction is typically predicted "taken". Therefore, the microcode unit will continually dispatch the loop microcode instructions until a functional unit detects a mispredicted branch. Because of the pipeline nature of the microprocessor, the branch misprediction is not detected by a functional unit for several clock cycles. In the interim between the end of the loop and detecting the branch misprediction, the microcode unit fills the instruction pipeline with microcode instructions that must be flushed. The overhead of issuing and flushing the unnecessary microcode instructions is considerable. The overhead is especially burdensome if the string count is relatively small.